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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009-2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. single-phase pwm regulator for imvp-6.5? mobile cpus and gpus isl62881, isl62881b the isl62881 is a single-phase pwm buck regulator for miroprocessor or graphics processor core power supply. it uses an integrated gate driver to provide a complete solution. the pwm modulator of isl62881 is based on intersil's robust ripple regulator (r 3 ) technology?. compared with traditional modulators, the r 3 ? modulator commands variable switching frequency during load transients, achieving faster transient response. with the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. the isl62881 can be configured as cpu or graphics vcore controller and is fully compliant with imvp-6.5 ? specifications. it responds to dprslpvr signals by entering/exi ting diode emulation mode. it reports the regulator output current through the imon pin. it senses the current by using either discrete resistor or inductor dcr whose variation over-temperature can be thermally compensated by a single ntc thermistor. it uses differential remote voltage sensing to accurately regulate the processor die voltage. the adaptive body di ode conduction time reduction function minimizes th e body diode conduction loss in diode emulation mode. user-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. maintaining all the isl62881 functions, the isl62881b offers vr_tt# function for thermal throttli ng control. it also offers the split lgate function to further improve light load efficiency. features ? precision core voltage regulation - 0.5% system accuracy over-temperature - enhanced load line accuracy ? voltage identification input - 7-bit vid input, 0v to 1.500v in 12.5mv steps - supports vid changes on-the-fly ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? superior noise immunity and transient response ? current monitor ? differential remote voltage sensing ? high efficiency across entire load range ? integrated gate driver ? split lgate driver to increase light-load efficiency (for isl62881b) ? adaptive body diode conduction time reduction ? user-selectable overshoot reduction function ? capable of disabling the droop function ? audio-filtering for gpu application ? small footprint 28 ld 4x4 tqfn package ? pb-free (rohs compliant) applications ? notebook computers ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl62881hrtz 628 81hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 ISL62881BHRTZ 62881b hrtz -10 to +100 32 ld 5x5 tqfn l32.5x5e notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl62881 , isl62881b . for more information on msl please see techbrief tb363 . june 16, 2011 fn6924.3
isl62881, isl62881b 2 fn6924.3 june 16, 2011 pin function descriptions gnd (bottom pad) signal common of the ic. unle ss otherwise stated, signals are referenced to the gnd pin. clk_en# open drain output to enable system pll clock; goes active 13 switching cycles after v core is within 10% of v boot . pgood power-good open-drain output in dicating when the regulator is able to supply regulated voltage. pull-up externally with a 680 resistor to vccp or 1.9k to 3.3v. rbias a resistor to gnd sets internal current reference. a 147k resistor sets the controller for cpu core application and a 47k resistor sets the controlle r for gpu core application. vr_tt# thermal overload output indicator. ntc thermistor input to vr_tt# circuit. vw a resistor from this pin to comp programs the switching frequency (8k gives approximately 300khz). comp this pin is the output of the error am plifier. also, a resistor across this pin and gnd adjusts the overcurrent threshold. fb this pin is the inverting input of the error amplifier. vsen remote core voltage sense input. connect to microprocessor die. rtn remote voltage sensing return. connect to ground at microprocessor die. isum- and isum+ droop current sense input. vdd 5v bias power. vin battery supply voltage, used for feed-forward. imon an analog output. imon outputs a current proportional to the regulator output current. boot connect an mlcc capacitor across the boot and the phase pins. the boot capacitor is charged through an internal boot pin configurations isl62881 (28 ld tqfn) top view isl62881b (32 ld tqfn) top view 1 28 2 3 4 5 6 7 21 20 19 18 17 16 15 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd pad (bottom) v i d 6 v i d 4 v i d 3 v i d 2 vid0 d p r s l p v r vccp lgate phase ugate comp fb vw pgood rbias clk_en# v i d 5 v r _ o n vssp isum- isum+ vin imon vdd rtn vsen boot vid1 1 32 2 3 4 5 6 7 24 23 22 21 20 19 18 31 30 29 28 27 26 9 101112131415 gnd pad (bottom) v r _ o n v i d 5 v i d 4 v i d 3 vid0 c l k _ e n # vccp lgatea phase gnd vw ntc rbias vr_tt# v i d 6 d p r s l p v r vssp isum- isum+ vin imon vdd vsen vid1 8 comp fb pgood boot 16 rtn 17 ugate lgateb 25 vid 2
isl62881, isl62881b 3 fn6924.3 june 16, 2011 diode connected from the vccp pin to the boot pin, each time the phase pin drops below vccp minus the voltage dropped across the internal boot diode. ugate output of the high-side mosfet gate driver. connect the ugate pin to the gate of the high-side mosfet. phase current return path for the high-side mosfet gate driver. connect the phase pin to the node consis ting of the high-side mosfet source, the low-side mosfet drain and the output inductor. vssp current return path for the low-side mosfet gate driver. connect the vssp pin to the source of the low-side mosfet through a low impedance path, preferably in pa rallel with the trace connecting the lgate pin to the gate of the low-side mosfet. lgate (for isl62881) output of the low-side mosfet gate driver. connect the lgate pin to the gate of the low-side mosfet. lgatea (for isl62881b) output of the low-side mosfet gate driver that is always active. connect the lgatea pin to the gate of the low-side mosfet that is active all the time. lgateb (for isl62881b) another output of the low-side mosfet gate driver. this gate driver will be pulled low when the dprslpvr pin logic is high. connect the lgateb pin to the gate of the low-side mosfet that is idle in deeper sleep mode. vccp input voltage bias for the internal gate drivers. connect +5v to the vccp pin. decouple with at le ast 1f of an mlcc capacitor to vssp1 and vssp2 pins respectively. vid0, vid1, vid2, vid3, vid4, vid5, vid6 vid input with vid0 = lsb and vid6 = msb. vr_on voltage regulator enable input. a high level logic signal on this pin enables the regulator. dprslpvr a high level logic signal on this pin puts the isl62881 in 1-phase diode emulation mode. if r bias = 47k (gpu vr application), this pin also controls v core slew rate. v core slews at 5mv/s for dprslpvr = 0 and 10mv/s for dprslpvr = 1. if r bias = 147k (cpu vr application), th is pin doesn?t control v core slew rate.
isl62881, isl62881b 4 fn6924.3 june 16, 2011 block diagram vid0 vid1 vid2 vid3 vid4 vid5 vid6 vr_on dprslpvr mode control dac and soft start rtn e/a fb idroop current sense isum+ isum- imon imon comp protection pgood clk_en# adj. ocp threshold vsen clock vw vin flt woc oc 2.5x woc oc vin vdac modulator vin vdac comp vw comp pgood and clk_en# logic gnd vdd rbias 60a
isl62881, isl62881b 5 fn6924.3 june 16, 2011 absolute maximum rating s thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . . phase-0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . . p hase-5v (<20ns pulse width, 10j) to boot lgate voltage (lgate). . . . . . . . . . . . . . . . . . . . . . -0.3v (dc) to vdd + 0.3v . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, vr_tt#, clk_en# . . . . . . . . . . . . . . -0.3v to +7v thermal resistance (typical, notes 4, 5) ja (c/w) jc (c/w) 28 ld tqfn package . . . . . . . . . . . . . . . . . . 40 3 32 ld tqfn package . . . . . . . . . . . . . . . . . . 32 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 1v 3.2 4.0 ma vr_on = 0v 1 a battery supply current i vin vr_on = 0v 1 a v in input resistance r vin vr_on = 1v 900 k power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v system and references system accuracy %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v -0.5 +0.5 % vid = 0.5v to 0.7375v -8 +8 mv vid = 0.3v to 0.4875v -15 +15 mv v boot 1.0945 1.100 1.1055 v maximum output voltage v cc_core(max) vid = [0000000] 1.500 v minimum output voltage v cc_core(min) vid = [1111111] 0 v r bias voltage r bias = 147k 1.45 1.47 1.49 v channel frequency nominal channel frequency f sw(nom) rf set = 7k , v comp =1v 295 310 325 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.15 +0.15 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz
isl62881, isl62881b 6 fn6924.3 june 16, 2011 power good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay tpgd clk_enable# low to pgood high 6.3 7.6 8.9 ms ugate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ugate source current i ugsrc boot - ugate = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate driver for isl62881 lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 lgate source current i lgsrc vccp - lgate = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns lgate drivers for isl62881b lgatea and b pull-up resistance r lgpu 250ma source current 2.0 3 lgatea and b source current i lgsrc vccp - lgatea and b = 2.5v 1.0 a lgatea and b sink resistance r lgpd 250ma sink current 1 1.8 lgatea and b sink current i lgsnk lgatea and b - vssp = 2.5v 2.0 a ugate to lgatea and b deadtime t ugflgr ugate falling to lgatea and b rising, no load 23 ns lgatea and b to ugate deadtime t lgfugr lgatea and b falling to ugate rising, no load 28 ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1ms 150 200 240 mv severe overvoltage threshold ov hs vsen rising for >2s 1.525 1.55 1.575 v oc threshold offset isum- pin current 8.2 10.1 12 a undervoltage threshold uv f vsen falling below setpoint for >1.2ms -355 -295 -235 mv logic thresholds vr_on input low v il(1.0v) 0.3 v vr_on input high v ih(1.0v) 0.7 v vid0-vid6 and dprslpvr input low v il(1.0v) 0.3 v vid0-vid6 and dprslpvr input high v ih(1.0v) 0.7 v thermal monitor (for isl62881b) ntc source current ntc = 1.3v 53 60 67 a electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62881, isl62881b 7 fn6924.3 june 16, 2011 over-temperature threshold v (ntc) falling 1.18 1.2 1.22 v vr_tt# low output resistance r tt i = 20ma 6.5 9 clk_en# output levels clk_en# low output voltage v ol i = 4ma 0.26 0.4 v clk_en# leakage current i oh clk_en# = 3.3v -1 1 a current monitor imon output current i imon isum- pin current = 20a 108 120 132 a isum- pin current = 10a 51 60 69 a isum- pin current = 5a 22 30 37.5 a imon clamp voltage v imonclamp 1.1 1.15 v current sinking capability 275 a inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 0 1 a vidx leakage current i vidx vidx = 0v -1 0a vidx = 1v 0.45 1 a dprslpvr leakage current i dprslpvr dprslpvr = 0v -1 0a dprslpvr = 1v 0.45 1 a slew rate slew rate (for vid change) sr 56.5 mv/s note: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62881, isl62881b 8 fn6924.3 june 16, 2011 gate driver timing diagram simplified application circuits figure 1. isl62881 typical application circuit using dcr sensing pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr (bottom pad) vss fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids rbias clk_en# v+5 vdd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881 r bias l v o r sum rn cn ri v in phase ugate boot lgate isum+ isum- vssp ris cis vin vin c
isl62881, isl62881b 9 fn6924.3 june 16, 2011 figure 2. isl62881 typical application circuit using resistor sensing simplified application circuits (continued) (bottom pad) vss fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids rbias clk_en# v+5 vdd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881 r bias cn ri vin phase ugate boot lgate isum+ isum- vssp ris cis vin vin l v o r sum rsen
isl62881, isl62881b 10 fn6924.3 june 16, 2011 figure 3. isl62881b typical application circuit using dcr sensing simplified application circuits (continued) gnd fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids r bias clk_en# v+5 v dd imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood v+5 vccp isl62881b r bias l v o rsum rn cn ri v in phase ugate boot lgatea isum+ isum- vssp o c ris cis v in v in ntc o c vr_tt# vr_tt# lgateb
isl62881, isl62881b 11 fn6924.3 june 16, 2011 figure 4. isl62881b typical application circuit using resistor sensing simplified application circuits (continued) vss v+5 v dd v+5 vccp isl62881b cn ri isum+ isum- ris cis v in v in l v o rsum rsen v in phase ugate boot lgatea vssp lgateb fb vsen comp r droop rf set vw rtn vr_on dprslpvr vids r bias clk_en# imon clk_en# vid<0:6> dprslpvr vr_on pgood r imon vss sense vcc sense imon pgood r bias ntc o c vr_tt# vr_tt#
isl62881, isl62881b 12 fn6924.3 june 16, 2011 theory of operation multiphase r 3? modulator the isl62881 is a single-phase regulator implementing intel ? imvp-6.5 ? protocol. it uses intersil patented r 3? (robust ripple regulator ? ) modulator. the r 3? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 5 conceptually shows the isl62881 r 3? modulator circuit, and figure 6 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between between the two pins. this voltage window is called vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuit. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot clock signal. the slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the isl62881 works with v crs , which is large-amplitude and noise-free synthesized sign al, the isl62881 achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the isl62881 has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. figure 7 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the clock signal more quickly, so the pwm pulse turns on earlier, increasing the effective switching frequency, which allows for higher control loop ba ndwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulse wider. during load release response, the comp voltage falls. it takes the master clock circuit longer to generate the next clock signal so the pwm pulse is held off until needed. the vw voltage falls as the vw voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl62881 excellent response speed. figure 5. r 3? modulator circuit crm gmvo master clock vw comp clock r il gm clock phase crs vw s q pwm l co vo vcrm vcrs master clock circuit slave circuit figure 6. r 3? modulator operation principles in steady state comp vcrm pwm vw clock hysteretic window vcrs vw figure 7. r 3? modulator operation principles in load insertion response comp vcrm pwm vcrs vw clock vw
isl62881, isl62881b 13 fn6924.3 june 16, 2011 diode emulation and period stretching isl62881 can operate in diode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and doesn?t not allow reverse current, emulating a diode. as shown in figure 8, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the isl62881 monitors the current through monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversin g the direction and creating unnecessary power loss. if the load current is light enough, as figure 9 shows, the inductor current will reach and stay at ze ro before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 9 shows the operation princi ple in diode emulation mode at light load. the load gets incrementally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the isl62881 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from ea ch other such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the 3.3v logic high threshold. figure 10 shows the typical start- up timing when the isl62881 is configured for cpu vr applicatio n. the isl62881 uses digital soft-start to ramp up dac to the boot voltage of 1.1v at about 2.5mv/s. once the output voltage is within 10% of the boot voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low and dac slews at 5mv/s to the voltage set by the vid pins. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. figure 11 shows the typical start- up timing when the isl62881 is configured for gpu vr application. the isl62881 uses digital soft-start to ramp-up dac to the voltage set by the vid pins at 5mv/s. once the output voltage is within 10% of the target voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low. pgood is asserted high in approximately 7ms. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. figure 8. diode emulation ugate phase il lgate figure 9. period stretching il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 10. soft-start wavefo rms for cpu vr application vdd vr_on dac 800s 2.5mv/s vboot 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms figure 11. soft-start waveforms for gpu vr application vdd vr_on dac 120s 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms
isl62881, isl62881b 14 fn6924.3 june 16, 2011 voltage regulation and load line implementation after the start sequence, the isl62881 regulates the output voltage to the value set by th e vid inputs per table 1. the isl62881 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. table 1. vid table vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 0 0 0 0 0 0 0 1.5000 00000011.4875 00000101.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 00001011.4375 0 0 0 0 1 1 0 1.4250 00001111.4125 0 0 0 1 0 0 0 1.4000 00010011.3875 00010101.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 00011011.3375 0 0 0 1 1 1 0 1.3250 00011111.3125 0 0 1 0 0 0 0 1.3000 00100011.2875 00100101.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 00101011.2375 0 0 1 0 1 1 0 1.2250 00101111.2125 0 0 1 1 0 0 0 1.2000 00110011.1875 00110101.1750 00110111.1625 0 0 1 1 1 0 0 1.1500 00111011.1375 00111101.1250 00111111.1125 01000001.1000 01000011.0875 01000101.0750 01000111.0625 01001001.0500 01001011.0375 01001101.0250 01001111.0125 01010001.0000 01010010.9875 01010100.9750 01010110.9625 01011000.9500 01011010.9375 01011100.9250 01011110.9125 01100000.9000 01100010.8875 01100100.8750 01100110.8625 01101000.8500 01101010.8375 01101100.8250 01101110.8125 01110000.8000 01110010.7875 01110100.7750 01110110.7625 01111000.7500 01111010.7375 01111100.7250 01111110.7125 10000000.7000 10000010.6875 10000100.6750 10000110.6625 10001000.6500 10001010.6375 10001100.6250 10001110.6125 10010000.6000 10010010.5875 10010100.5750 10010110.5625 10011000.5500 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v)
isl62881, isl62881b 15 fn6924.3 june 16, 2011 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the isl62881 can sense the inductor current through the intrinsic dc resistance (dcr) resistance of the inductors as shown in figure 1 or through resistors in series with the inductors as shown in figure 2. in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. figure 12 shows the load line implementation. the isl62881 drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop, as shown in equation 2. 10011010.5375 10011100.5250 10011110.5125 10100000.5000 10100010.4875 10100100.4750 10100110.4625 10101000.4500 10101010.4375 10101100.4250 10101110.4125 10110000.4000 10110010.3875 10110100.3750 10110110.3625 10111000.3500 10111010.3375 10111100.3250 10111110.3125 11000000.3000 11000010.2875 11000100.2750 11000110.2625 11001000.2500 11001010.2375 11001100.2250 11001110.2125 11010000.2000 11010010.1875 11010100.1750 11010110.1625 1 1 0 1 1 0 0 0.1500 11011010.1375 11011100.1250 11011110.1125 11100000.1000 11100010.0875 11100100.0750 11100110.0625 11101000.0500 11101010.0375 11101100.0250 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 11101110.0125 11110000.0000 11110010.0000 11110100.0000 11110110.0000 11111000.0000 11111010.0000 11111100.0000 11111110.0000 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) figure 12. differential sensing and load line implementation x 1 e/a i droop 2xv cn r i ---------------- = (eq. 1) v droop r droop i droop = (eq. 2)
isl62881, isl62881b 16 fn6924.3 june 16, 2011 v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 12 also shows the differ ential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity gain differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and the non-inverting input voltages to be equal, therefore: rewriting equation 3 and substituting equation 2 gives: equation 4 is the exact equa tion required for load line implementation. the vcc sense and vss sense signals come fr om the processor die. the feedback will be open circuit in the absence of the processor. as shown in figure 12, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?cat ch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. ccm switching frequency the r fset resistor between the comp and the vw pins sets the vw windows size, which therefore sets the switching frequency. when the isl62881 is in continuo us conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3? modulator. as explained in ?multiphase r3? modulator? on page 12, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. eq uation 5 gives an estimate of the frequency-setting resistor r fset value. 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. modes of operation table 2 shows the isl62881 operational modes, programmed by the logic status of the dprslp vr pin. the isl62881 enters 1-phase de mode when there is dprslpvr = 1. when the isl62881 is configured for gpu vr application, dprslpvr logic status also cont rols the output voltage slew rate. the slew rate is 5mv/s for dprslpvr = 0 and is 10mv/s for dprslpvr = 1. dynamic operation when the isl62881 is configured for cpu vr application, it responds to vid changes by sl ewing to the new voltage at 5mv/s slew rate. as the output approaches the vid command voltage, the dv/dt moderates to prevent overshoot. geyserville-iii transitions commands one lsb vid step (12.5mv) every 2.5s, controlling the effective dv/d t at 5mv/s. the isl62881 is capable of 5mv/s slew rate. when the isl62881 is configured for gpu vr application, it responds to vid changes by slewin g to the new voltage at a slew rate set by the logic status on the dprslpvr pin. the slew rate is 5mv/s when dprslpvr = 0 and is 10mv/s when dprslpvr = 1. when the isl62881 is in de mode, it will actively drive the output voltage up when the vid changes to a higher value. it?ll resume de mode operation afte r reaching the new voltage level. if the load is light enough to warrant dcm, it will enter dcm after the inductor current has crossed zero for four consecutive cycles. the isl62881 will remain in de mo de when the vid changes to a lower value. the output voltage will decay to the new value and the load will determine the slew rate. the r 3? modulator intrinsically has voltage feed forward. the output voltage is insensitive to a fast slew rate input voltage change. protections the isl62881 provides overcurrent, undervoltage, and overvoltage protections. the isl62881 determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold. it declares ocp when i droop is above the threshold for 120s. a resistor r comp from the comp pin to gnd programs the ocp current source threshold, as well as the overshoot reduction function (to be discussed in later sections), as table 3 shows. it is reco mmended to use the nominal r comp value. the isl62881 detects the r comp value at the beginning of start-up, and sets the internal ocp threshold accordingly. it remembers the r comp value until the vr_on signal drops below the por threshold. vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) r fset k () period s () 0.29 ? () 2.65 = (eq. 5) table 2. isl62881 modes of operation configuration dprslpvr operational mode voltage slew rate cpu vr application 0 1-phase ccm 5mv/s 1 1-phase de gpu vr application 0 1-phase ccm 5mv/s 1 1-phase de 10mv/s
isl62881, isl62881b 17 fn6924.3 june 16, 2011 the default ocp threshold is the value when r comp is not populated. it is recommended to scale the droop current i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. for overcurrent condition above 2.5x the ocp level, the pwm output will immediately shut off and pgood will go low to maximize protection. this protec tion is also referred to as way-overcurrent protection or fa st-overcurrent protection, for short-circuit protections. the isl62881 will declare undervoltage (uv) fault and latch-off if the output voltage is less than the vid set value by 300mv or more for 1ms. it?ll turn off the pwm output and de-assert pgood. the isl62881 has two levels of overvoltage protections. the first level of overvoltage protection is referred to as pgood overvoltage protection. if the output voltage exceeds the vid set value by +200mv for 1ms, the is l62881 will declare a fault and de-assert pgood. the isl62881 takes the same actions for all of the above fault protections: de-assertion of pgood and turn-off of the high-side and low-side power mosfets. any residual inductor current will decay through the mosfet body diodes. these fault conditions can be reset by bringing vr _on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. the second level of overvoltage protection is different. if the output voltage exceeds 1.55v, the isl62881 will immediately declare an ov fault, de-assert pg ood, and turn on the low-side power mosfets. the low-side power mosfets remain on until the output voltage is pulled down below 0.85v when all power mosfets are turned off. if the output voltage rises above 1.55v again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. resetting vr_on cannot clear the 1.55v ovp. only resetting v dd will clear it. the 1.55v ovp is active all the time when the controller is enabled, even if on e of the other faults have been declared. this ensures that the processor is protected against high-side power mosfet leakage while the mosfets are commanded off. table 4 summarizes the fault protections. current monitor the isl62881 provides the current monitor function. the imon pin outputs a high-speed analog cu rrent source that is 3 times of the droop current flowing out of the fb pin. thus as shown by equation 6. as figures 1 and 2 show, a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor can be paralleled with r imon to filter the voltage information. the imvp-6.5 ? specification requires that the imon voltage information be referenced to vss sense . the imon pin voltage range is 0v to 1.1v. a clamp circuit prevents the imon pin voltage from going above 1.1v. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the lo w-side mosfet turns off, it?ll flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it?ll flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator threshold volt age accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. table 3. isl62881 ocp threshold and overshoot reduction function r comp ocp threshold (a) overshoot reduction function min (k ) nominal (k ) max (k ) none none 20 disabled 305 400 410 22.67 205 235 240 20.67 155 165 170 18 104 120 130 20 enabled 78 85 90 22.67 62 66 68 20.67 45 50 55 18 table 4. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent (2.5xoc) <2s overvoltage +200mv 1ms undervoltage -300mv overvoltage 1.55v immediately low-side mosfet on until v core <0.85v, then pwm tri-state, pgood latched low. vdd toggle i imon 3i droop = (eq. 6)
isl62881, isl62881b 18 fn6924.3 june 16, 2011 overshoot reduction function the isl62881 has an optional overshoot reduction function, enabled or disabled by the resistor from the comp pin to gnd, as shown in table 3. when a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. the inductor current freewheels through the low-side mosfet during this period of time. the overshoot reduction function turns off the low-side mosfet during the output voltage overshoot, forcing the inductor current to freewheel through the low-side mosfet body diode. si nce the body diode voltage drop is much higher than mosfet r ds(on) voltage drop, more energy is dissipated on the low-side mosfet therefore the output voltage overshoot is lower. if the overshoot reduction function is enabled, the isl62881 monitors the comp pin voltage to determine the output voltage overshoot condition. the comp voltage will fall and hit the clamp voltage when the output voltage overshoots. the isl62881 will turn off lgate when comp is being clamped. the low-side mosfet in the power stage will be turned off. when the output voltage has reached its peak and starts to come down, the comp voltage starts to rise and is no longer clamped. the isl62881 will resume normal pwm operation. while the overshoot reduction function reduces the output voltage overshoot, energy is dissi pated on the low-side mosfet, causing additional power loss. the more frequent the transient event, the more power loss is dissipated on the low-side mosfet. the mosfet may face severe thermal stress when transient events happen at a high repetitive rate. user discretion is advised when this function is enabled. key component selection r bias the isl62881 uses a resistor (1% or better tolerance is recommended) from the rbias pin to gnd to establish highly accurate reference current sources inside the ic. using r bias =147k sets the controller for cpu core application and using r bias = 47k sets the controller for gpu core application. do not connect any other components to this pin. do not connect any capacitor to the rbias pin as it will create instability. care should be taken in layout that the resistor is placed very close to the rbias pin and that a good quality signal ground is connected to the opposite side of the r bias resistor. r is and c is as figures 1 and 2 show, the isl62881 needs the r is - c is network across the isum+ and the isum- pins to stabilize the droop amplifier. the preferred values are r is = 82.5 and c is = 0.01f. slight deviations from the recommended values are acceptable. large deviations may result in instability. inductor dcr current-sensing network figure 13 shows the inductor dcr current-sensing network for a 2-phase solution. an inductor cu rrent flows through the dcr and creates a voltage drop. the inductor has a resistors in r sum connected to the phase-node-side pad and a pcb trace connected to the output-side pad to accurately sense the inductor current by sensing the dcr voltage drop. the sensed current information is fed to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor current information is presented to the capacitor c n . equations 7 through 11 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s): transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decreases as its temp erature decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represents the inductor total dc current over the temperature range of interest. cn rsum rntcs rntc rp dcr l phase io ri isum+ isum- vcn + - figure 13. dcr current-sensing network v cn s () r ntcnet r ntcnet r sum + ---------------------------------------- - dcr ?? ?? ?? i o s () a cs s () = (eq. 7) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 8) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 9) l dcr l ----------- - = (eq. 10) sns 1 r ntcnet r sum r ntcnet r sum + ---------------------------------------- - c n ------------------------------------------------------ = (eq. 11)
isl62881, isl62881b 19 fn6924.3 june 16, 2011 there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has higher signal level to work with. a typical set of parameters th at provide good temperature compensation are: r sum = 3.65k , r p =11k , r ntcs =2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltage drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient resp onse. transfer function a cs (s) has a pole sns and a zero l . one needs to match l and sns so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 12 gives c n value. for example, given r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 1.1m and l = 0.45h, equation 12 gives c n = 0.18f. assuming the compensator design is correct, figure 14 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 15 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 16 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. figure 17 shows the output voltage ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenomenon is not observed when the output capacitors have very low esr and esl, such as all ceramic capacitors. c n l r ntcnet r sum r ntcnet r sum + ---------------------------------------- - dcr ----------------------------------------------------------- - = (eq. 12) figure 14. desired load transient response waveforms o i v o figure 15. load transient response when c n is too small o i v o figure 16. load transient response when c n is too large o i v o figure 17. output voltage ring back problem i o v o i l ring back figure 18. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional + -
isl62881, isl62881b 20 fn6924.3 june 16, 2011 figure 18 shows two optional circ uits for reduction of the ring back. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100w. c ip should be determined through tuning the load transient response wavefo rms on an actual board. the recommended range for c ip is 100pf~2000pf. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 18 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional component to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 15 explains, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. resistor current-sensing network figure 19 shows the resistor current-sensing network. the inductor has a series current-sensing resistor r sen . r sum and is connected to the r sen pad to accurately capture the inductor current information. the r sum feeds the sensed information to capacitor c n . r sum and c n form a a filter for noise attenuation. equations 13 through 15 gives v cn (s) expressions: transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. overcurrent protection referring to equation 1 and figures 12, 13 and 19, resistor r i sets the droop current i droop . table 3 shows the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshol d is 20a. we will design i droop to be 14a at full load, so the ocp trip level is 1.43x of the full load current. for inductor dcr sensing, equation 16 gives the dc relationship of v cn (s) and i o (s). substitution of equation 16 into equation 1 gives: therefore: substitution of equation 8 and application of the ocp condition in equation 18 gives: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sum = 3.65k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 1.1m , i omax = 14a and i droopmax = 14a, equation 19 gives r i = 1.36k . for resistor sensing, equation 20 gives the dc relationship of v cn (s) and i o (s). cn rsum dcr l phase io ri isum+ isum- vcn rsen figure 19. resistor cu rrent-sensing network v cn s () r sen i o s () a rsen s () = (eq. 13) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 14) rsen 1 r sum c n -------------------------- - = (eq. 15) v cn r ntcnet r ntcnet r sum + ---------------------------------------- - dcr ?? ?? ?? i o = (eq. 16) i droop 2 r i ---- - r ntcnet r ntcnet r sum + ---------------------------------------- - dcr i o = (eq. 17) r i 2r ntcnet dcr i o r ntcnet r sum + () i droop -------------------------------------------------------------------- - = (eq. 18) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum + ?? ?? ?? i droopmax -------------------------------------------------------------------------------------------------------------- - = (eq. 19)
isl62881, isl62881b 21 fn6924.3 june 16, 2011 substitution of equation 20 into equation 1 gives equation 21: therefore : substitution of equation 22 and application of the ocp condition in equation 18 give s: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given r sen =1m , i omax = 14a and i droopmax = 14a, equation 23 gives r i = 2k . a resistor from comp to gnd can adjust the internal ocp threshold, providing another dimension of fine-tune flexibility. table 3 shows the detail. it is recommended to scale i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. load line slope refer to figure 12. for inductor dcr sensing, substitution of equation 17 into equation 2 gives the load line slope expression in equation 24. for resistor sensing, substitution of equation 21 into equation 2 gives the load line slope expression in equation 25 : substitution of equation 18 and rewriting equation 24, or substitution of equation 22 and rewriting equation 25 gives the same result in equation 26 : one can use the full load condition to calculate r droop . for example, given i omax = 14a, i droopmax = 14a and ll = 7m , equation 26 gives r droop = 7k . it is recommended to start with the r droop value calculated by equation 26, and fine tune it on the actual board to get accurate load line slope. one should record the output volt age readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. current monitor referring to equation 6 for the imon pin current expression. refer to figures 1 and 2, the imon pin current flows through r imon . the voltage across r imon is shown in equation 27: rewriting equation 26 gives equation 28: substitution of equation 28 into equation 27 gives equation 29: rewriting equation 29 and applicat ion of full load condition gives equation 30: for example, given ll = 7m , r droop = 7k , v rimon = 963mv at i omax = 14a, equation 30 gives r imon = 22.9k . a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. it is recommended to have a time constant long enough such that switching frequency ripples are removed. compensator figure 14 shows the desired load transient response waveforms. figure 20 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e. constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 21 conceptually shows t1(s) measurement set-up and figure 22 conceptually shows t2(s) measur ement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measur ed on an isl62881 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. v cn r sen i o = (eq. 20) i droop 2 r i ---- - r sen i o = (eq. 21) r i 2r sen i o i droop --------------------------- = (eq. 22) r i 2r sen i omax i droopmax -------------------------------------- = (eq. 23) ll v droop i o ----------------- - 2r droop r i ---------------------- r ntcnet r ntcnet r sum + ---------------------------------------- - dcr == (eq. 24) ll v droop i o ----------------- - 2r sen r droop r i ----------------------------------------- == (eq. 25) r droop i o i droop --------------- - ll = (eq. 26) v rimon 3i droop r imon = (eq. 27) i droop i o r droop ------------------ ll = (eq. 28) v rimon 3i o ll r droop -------------------- - r imon = (eq. 29) r imon v rimon r droop 3i o ll -------------------------------------------- = (eq. 30) figure 20. voltage regulator equivalent circuit i o v o vid z out(s) = ll load vr + -
isl62881, isl62881b 22 fn6924.3 june 16, 2011 t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. optional slew rate compensation circuit for 1-tick vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate of 2.5s or 1.25s per tick (12.5mv), controlling output voltage v core slew rate at 5mv/s or 10mv/s. figure 23 shows the waveforms of 1-tick vid transition. during 1-tick vid transition, the dac ou tput changes at approximately 15mv/s slew rate, but the dac cannot step through multiple vids to control the slew rate. instead, the control loop response speed determines v core slew rate. ideally, v core will follow the fb pin voltage slew rate. however, the controller senses the inductor current increase during th e up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to control v core slew rate during 1-tick vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . when v core increases, the time do main expression of the induced i droop change is as shown in equation 31 : figure 21. loop gain t1(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + - + + figure 22. loop gain t2(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + - figure 23. optional slew rate compensation circuit for1-tick vid transition x 1 e/a i droop t () c out ll r droop ------------------------ dv core dt ----------------- - 1e t ? c out ll ------------------------- ? ?? ?? ?? ?? = (eq. 31)
isl62881, isl62881b 23 fn6924.3 june 16, 2011 where c out is the total output capacitance. in the meantime, the r vid -c vid branch current i vid time domain expression is as shown in equation 32: it is desired to let i vid (t) cancel i droop_vid (t). so there are : and : the result is: and : for example: given ll = 3m , r droop = 4.22k , c out = 1320f, dv core /dt = 5mv/s and dv fb /dt = 15mv/s, equation 35 gives r vid = 4.22k and equation 36 gives c vid =227pf. it?s recommended to select the calculated r vid value and start with the calculated c vid value and tweak it on the actual board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual ground in small signal sense. the r vid -c vid network is between the vi rtual ground and the real ground, and hence has no affe ct on transient response. voltage regulator thermal throttling figure 24 shows the thermal throttling feature with hysteresis. an ntc network is connected between the ntc pin and gnd. at low temperature, sw1 is on and sw2 connects to the 1.20v side. the total current flowing out of the ntc pin is 60a. the voltage on ntc pin is higher than the threshold voltage of 1.20v and the comparator output is low. vr_tt# is pulled up by the external resistor. when temperature increases, th e ntc thermistor resistance decreases so the ntc pin voltage drops. when the ntc pin voltage drops below 1.20v, the co mparator changes polarity and turns sw1 off and throws sw2 to 1.24v. this pulls vr_tt# low and sends the signal to start thermal throttle. there is a 6a current reduction on ntc pin and 40mv voltage increase on threshold voltage of the comparat or in this state. the vr_tt# signal will be used to change the cpu operation and decrease the power consumption. when the temperature drops down, the ntc thermistor voltage will go up. if ntc voltage increases to above 1.24v, the comparator w ill flip back. the external resistance difference in thes e two conditions is shown in equation 37: one needs to properly select the ntc thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. a regular resist or may need to be in series with the ntc thermistor to meet the threshold voltage values. for example, given panasonic ntc thermistor with b = 4700, the resistance will drop to 0.03322 of its nominal at +105c, and drop to 0.03956 of its nominal at +100c. if the required temperature hysteresis is +105c to +100c, the required resistance of ntc will be as shown in equation 38: therefore, a larger value thermistor such as 470k ntc should be used. at +105c, 470k ntc resistance becomes (0.03322 470k ) = 15.6k . with 60a on the ntc pin, the voltage is only (15.6k 60a) = 0.937v. this value is much lower than the threshold voltage of 1.20v. therefore, a regular resistor needs to be in series with the ntc. the required resistance can be calculated by equation 39: 4.42k is a standard resistor value. therefore, the ntc branch should have a 470k ntc and 4.42k resistor in series. the part number for the ntc thermistor is ertj0ev474 j. it is a 0402 package. ntc thermistor will be placed in the hot spot of the board. layout guidelines table 5 shows the layout considerations. the designators refer to the reference designs shown in figures 25 and 26. i vid t () c vid dv fb dt ----------- - 1e t ? r vid c vid ------------------------------ ? ?? ?? ?? ?? = (eq. 32) c vid dv fb dt ----------- - c out ll r droop ------------------------ dv core dt ----------------- - = (eq. 33) r vid c vid c out ll = (eq. 34) r vid r droop = (eq. 35) c vid c out ll r droop ------------------------ dv core dt ----------------- - dv fb dt ----------- - ----------------- - = (eq. 36) ntc r ntc - + v ntc - + vr_tt# 1.24v 54a internal to isl62881 figure 24. circuitry associated with the thermal throttling feature of the isl62881 r s 64a 1.20v sw1 sw2 1.24v 54 a --------------- 1.20v 60 a --------------- ? 2.96k = (eq. 37) (eq. 38) 2.96k 0.03956 0.03322 ? () ------------------------------------------------------- 467k = (eq. 39) 1.20v 60 a --------------- 15.6k ? 4.4k =
isl62881, isl62881b 24 fn6924.3 june 16, 2011 table 5. layout considerations name layout consideration gnd create analog ground plane underneath the controller and the analog signal proces sing components. don?t let the power ground plane overlap with the analog ground plane. avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the anal og plane. clk_en# no special consideration. pgood no special consideration. rbias place the r bias resistor (r 16 ) in general proximity of the controller. low impedance connection to the analog ground plane. vr_tt# no special consideration. ntc the ntc thermistor (r9) needs to be placed close to the ther mal source that is monitor to determine thermal throttling. usua lly it?s placed close to phase-1 high-side mosfet. vw place capacitor (c4) across vw and comp in close proximity of the controller. comp place compensator components (c3, c5, c6 r7, r11, r10 and c11) in general proximity of the controller. fb vsen place the vsen/rtn filter (c12, c13) in clos e proximity of the controller for good decoupling. rtn vdd a capacitor (c16) decouples it to gnd. pl ace it in close proximity of the controller. imon place the filter capacitor (c21) close to the cpu. isum- place the current sensing circuit in general proximity of the controller. place c82 very close to the controller. place ntc thermistors r 42 next to inductor (l1) so it senses the inductor temperature correctly. the power stage sends a pair of vsum+ and vsum- signals to the co ntroller. run these two signal traces in parallel fashion with decent width (>20mil). important: sense the inductor current by rout ing the sensing circuit to the inductor pads. route r 63 to the phase-node side pad of inductor l1. route the other current sensing trace to the output side pad of inductor l1. if possible, route the traces on a different layer from the indu ctor pad layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces in to the pads from the inside of the inductor. the following drawi ngs show the two preferred ways of rout ing current sensing traces. isum+ vin a capacitor (c17) decouples it to gnd. pl ace it in close proximity of the controller. boot use decent wide trace (>30mil). avoid any sensitive an alog signal trace from cros sing over or getting close. ugate run these two traces in parallel fash ion with decent width (>30mil). avoid any se nsitive analog signal trace from crossing over or getting close. recommend routing phase trace to the high-side mosfet (q2 and q8) source pins instead of general phase node copper. phase vssp run these two traces in parallel fashio n with decent width (>30mil). avoid any sens itive analog signal trace from crossing over or getting close. recommend routing vssp to the low-side mosfet (q3 and q9 ) source pins instead of general power ground plane for better performance. lgate or lgatea and lgateb vccp a capacitor (c22) decouples it to gnd. pl ace it in close proximity of the controller. vid0~6 no special consideration. vr_on no special consideration. dprslpvr no special consideration. phase node minimize phase node copper area. don?t let the phase node copper overlap wi th/getting close to other sensitive traces . cut the power ground plane to avoid overlapping with phase node copper. minimize the loop consisti ng of input capacitor, high-side mosfets and low-side mosfets (e.g.: c27, c33, q2, q8, q3 and q9). inductor current- sensing traces vias inductor current- sensing traces
isl62881, isl62881b 25 fn6924.3 june 16, 2011 3900pf place near l1 ------------ optional ---- dnp dnp -------- ---- optional ------- ---- 270pf 470uf dnp tbd ---- ------- ---- optional ---- ----- 422k ---- dnp ---- ------------ 330pf 2.37k 6.98k dnp 0.15uf 0.88uh 15pf 47k 0.1uf -----> 0.01uf 11k ntc 10k 2.61k 22.6k 3.65k irf7832 irf7821 layout note: 82.5 3.01k 0.056uf optional ----- route ugate trace in parallel 10k with the phase trace going to the source of q2 route lgate trace in parallel with the vssp trace going to the source of q3 1000pf 100pf -------- 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf c11 r23 1.91k r19 26 isl62881hrz c12 vccsense r20 c81 r109 l1 r56 c6 c16 r10 r11 c15 0.22uf c3 vsssense vcore +5v vr_on vid2 vid6 vid5 vid3 vid1 vid0 vin 10 r17 r7 c4 0 18 22 16 8 9 21 u6 24 28 19 17 3 4 1 5 6 7 10 11 12 13 14 15 20 2 r30 c20 r26 c82 1uf c17 1 vin r38 r42 r41 r63 r50 c21 vid4 0 c30 0.22uf 56uf c24 10uf c27 10uf c33 q3 q2 c54 vcore c61 c60 c41 c40 c56 c52 c55 10 1000pf 23 29 r16 r6 c22 1uf 0 r40 r37 27 +5v r18 r4 c13 25 dprslpvr +3.3v pgood r110 c83 c18 vsssense c59 imon ep vid6 vid5 vid4 dprslpvr vccp lgate vssp vr_on rbias vw clk_en# comp fb vsen rtn isum- isum+ vdd vin imon boot ugate phase vid0 vid1 vid2 vid3 pgood out out in in in in in in in out in in in in in in in in in in in figure 25. gpu application reference design
isl62881, isl62881b 26 fn6924.3 june 16, 2011 2700pf with the vssp trace going to route ugate trace in parallel 10uf 10uf the source of q2 and q8 the source of q3 and q9 ---- ----------- 0.01uf optional ---- ------- optional ---- ----- dnp dnp 1.91k ----------- 82.5 0.022uf ----- ---- 1000pf irf7821 route lgate trace in parallel 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf layout note: with the phase trace going to 330uf 330uf 4.87k -----> 11k 0.1uf 10k ntc irf7832 irf7832 0.45uh 3.65k 2.61k 34k 4.22k 470pf 27pf 100pf 422k 330pf place near l1 10uf 0.15uf ---- 7.32k dnp dnp dnp ------- ---- ---- ---- -------- -------- optional optional c11 18 19 14 r37 c17 r110 c83 c13 r4 c30 +3.3v vsssense r41 c60 c67 q3 r30 c82 r11 clk_en# 1.91k r23 pgood 10k r19 vid0 vid2 c81 r109 0.22uf 13 isl62881hrz 1uf 15 16 0 1 r17 c3 c4 r6 vcore c68 c66 c65 c64 c43 c42 c50 c55 c54 c61 c75 c59 c49 c48 c74 c41 c71 c40 c63 c47 c70 c56 c52 0.22uf c24 c27 +5v c16 vin 56uf 0 10uf c33 10uf q9 1uf c22 vid1 vid3 vid5 vid6 vr_on dprslpvr vid4 r16 147k r10 2 23 20 10 7 5 1 29 4 3 17 28 25 u6 0 c21 r50 r40 +5v 21 9 8 r20 22 r42 c20 l1 q2 c39 vcore 26 27 r38 r56 r63 vsssense vccsense vin imon 12 11 c18 10 1000pf c12 c6 r18 r7 r26 c15 24 6 10 ep vid6 vid5 vid4 dprslpvr vccp lgate vssp vr_on rbias vw clk_en# comp fb vsen rtn isum- isum+ vdd vin imon boot ugate phase vid0 vid1 vid2 vid3 pgood in in in in in in in out in in in in in in in in in in out in out out figure 26. cpu application reference design
isl62881, isl62881b 27 fn6924.3 june 16, 2011 cpu application reference de sign bill of materials qty reference value description manufacturer part number package 1 c11 470pf multilayer cap, 16v, 10% generic h1045-00471-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 1 c15 0.01f multilayer cap, 16v, 10% generic h1045-00103-16v10 sm0603 2 c16, c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.15f multilayer cap, 16v, 10% generic h1045-00154-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 1 c21 2700pf multilayer cap, 16v, 10% generic h1045-00272-16v10 sm0603 2 c17, c30 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 1 c24 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 2 c27, c33 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 100pf multilayer cap, 16v, 10% generic h1045-00101-16v10 sm0603 2 c39, c52 330f spcap, 2v, 4m panasonic eexsx0d331e4 polymer cap, 2.5v, 4.5m kemet t520v337m2r5a(1)e4r5-6666 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 30 c40-c43, c47-c50, c53-c56, c59, c75, c78 10f multilayer cap, 6.3v, 20% murata grm21br61c106ke15l sm0805 tdk c2012x5r0j106k 1 c6 27pf multilayer cap, 16v, 10% generic h1045-00270-16v10 sm0603 1 c82 0.022f multilayer cap, 16v, 10% generic h1045-00223-16v10 sm0603 0c81, c83 dnp 1 l1 0.45h inductor, inductance 20%, dcr 7% nec-tokin mpcg1040lr45 10mmx10mm 1 q2 n-channel power mosfet ir irf7821 pwrpakso8 2 q3, q9 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 4.87k thick film chip resistor, 1% generic h2511-04871-1/16w1 sm0603 1 r11 4.22k thick film chip resistor, 1% generic h2511-04221-1/16w1 sm0603 1 r16 147k thick film chip resistor, 1% generic h2511-01473-1/16w1 sm0603 2 r17, r18 10 thick film chip resistor, 1% generic h2511-00100-1/16w1 sm0603 1 r19 1.91k thick film chip resist or, 1% generic h2511-01911-1/16w1 sm0603 1 r26 82.5 thick film chip resist or, 1% generic h2511-082r5-1/16w1 sm0603 3 r20, r40, r56 0 thick film chip resi stor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 1.91k thick film chip resist or, 1% generic h2511-01911-1/16w1 sm0603 1 r37 1 thick film chip resistor , 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor, 1% generic h2511-01102-1/16w1 sm0603 1 r41 2.61k thick film chip resistor, 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 34k thick film chip resistor, 1% generic h2511-03402-1/16w1 sm0603
isl62881, isl62881b 28 fn6924.3 june 16, 2011 1 r6 7.32k thick film chip resistor, 1% generic h2511-07321-1/16w1 sm0603 1 r63 3.65k thick film chip resistor, 1% generic h2511-03651-1/16w1 sm0805 1 r7 422k thick film chip resistor, 1% generic h2511-04223-1/16w1 sm0603 0 r109, r110, r4, r8, r9 dnp 1 u6 imvp-6.5 pwm controller intersil isl62881hrtz qfn-28 cpu application reference de sign bill of materials (continued) qty reference value description manufacturer part number package gpu application reference de sign bill of materials qty reference value description manufacturer part number package 1 c11 270pf multilayer cap, 16v, 10% generic h1045-00271-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 1 c15 0.01f multilayer cap, 16v, 10% generic h1045-00103-16v10 sm0603 2 c16, c22 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.15f multilayer cap, 16v, 10% generic h1045-00154-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 2 c17, c30 0.22f multilayer cap, 25v, 10% generic h1045-00224-25v10 sm0603 1 c21 3900pf multilayer cap, 16v, 10% generic h1045-00392-16v10 sm0603 1 c24 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 2 c27, c33 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 100pf multilayer cap, 16v, 10% generic h1045-00101-16v10 sm0603 1 c52 470f spcap, 2v, 4m panasonic eexsx0d471e4 polymer cap, 2.5v, 4.5m kemet t520v477m2r5a(1)e4r5-6666 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 8 c40, c41, c54-c56, c59-c61 10f multilayer cap, 6.3v, 20% murata grm21br61c106ke15l sm0805 tdk c2012x5r0j106k 1 c6 15pf multilayer cap, 16v, 10% generic h1045-00150-16v10 sm0603 1 c82 0.056f multilayer cap, 16v, 10% generic h1045-00563-16v10 sm0603 0c81, c83 dnp 1 l1 0.88h inductor, inductance 20%, dcr 7% nec-tokin mpc1040lr88 10mmx10mm 1 q2 n-channel power mosfet ir irf7821 pwrpakso8 2 q3, q9 n-channel power mosfet ir irf7832 pwrpakso8 1 r10 2.37k thick film chip resistor , 1% generic h2511-02371-1/16w1 sm0603 1 r11 6.98k thick film chip resistor , 1% generic h2511-06981-1/16w1 sm0603 1 r16 47.5k thick film chip resistor , 1% generic h2511-04752-1/16w1 sm0603 2 r17, r18 10 thick film chip resistor , 1% generic h2511-00100-1/16w1 sm0603 1 r19 1.91k thick film chip resistor , 1% generic h2511-01911-1/16w1 sm0603 1 r26 82.5 thick film chip resistor , 1% generic h2511-082r5-1/16w1 sm0603
isl62881, isl62881b 29 fn6924.3 june 16, 2011 3 r20, r40, r56 0 thick film chip resi stor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 3.01k thick film chip resistor , 1% generic h2511-03011-1/16w1 sm0603 1 r37 1 thick film chip resistor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor, 1% generic h2511-01102-1/16w1 sm0603 1 r41 2.61k thick film chip resistor , 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 22.6k thick film chip resistor, 1% generic h2511-02262-1/16w1 sm0603 1 r6 10k thick film chip resistor, 1% generic h2511-01002-1/16w1 sm0603 1 r63 3.65k thick film chip resistor , 1% generic h2511-03651-1/16w1 sm0805 1 r7 412k thick film chip resistor , 1% generic h2511-04123-1/16w1 sm0603 0 r109, r110, r4, r8, r9 dnp 1 u6 imvp-6.5 pwm controller intersil isl62881hrtz qfn-28 gpu application reference de sign bill of materials (continued) qty reference value description manufacturer part number package
isl62881, isl62881b 30 fn6924.3 june 16, 2011 typical performance figure 27. cpu application ccm efficiency, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 28. cpu application dcm efficiency, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 29. cpu application ccm load line, vid = 0.9v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 30. cpu mode clk_en# delay, v in = 19v, i o =0a, vid = 1.2v, ch1: phase1, ch2: v o , ch4: clk_en# figure 31. cpu mode soft-start, v in = 19v, i o =0a, vid = 1.2v, ch1: phase, ch2: v o figure 32. gpu mode soft-start, v in =19v, i o =0a, vid = 1.2v, ch1: phase, ch2: v o 70 72 74 76 78 80 82 84 86 88 90 0 2 4 6 8 10121416182022 i out (a) efficiency (%) v in = 8v v in = 19v v in = 12v 70 72 74 76 78 80 82 84 86 88 0.1 1.0 10.0 i out (a) efficiency (%) v in = 8v v in = 19v v in = 12v 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 10 12 14 16 18 20 22 i out (a) v out (v) 02468 v in = 19v v in = 12v v in = 8v
isl62881, isl62881b 31 fn6924.3 june 16, 2011 figure 33. cpu mode shut down, v in =19v, i o =0a, vid = 1.2v, ch1: phase, ch2: v o figure 34. gpu mode shut down, v in = 19v, i o =0a, vid = 1.2v, ch1: phase, ch2: v o figure 35. ccm steady state, cpu mode, v in =8v, i o =1a, vid = 1.2375v, ch1: phase, ch2: v o figure 36. dcm steady state, cpu mode, v in =12v, i o =1a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: comp, ch4: lgate figure 37. gpu mode reference design loop gain t2(s) measurement result figure 38. imon, vid = 1.2375 typical performance (continued) gain phase margin 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 16 18 20 22 i out (a) imon-vsssense (mv) imon target
isl62881, isl62881b 32 fn6924.3 june 16, 2011 figure 39. load transient response with overshoot reduction function disabled, gpu mode, v in = 12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 40. load transient response with overshoot reduction function disabled, gpu mode, v in = 12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 41. load transient response with overshoot reduction function disabled, gpu mode, v in = 12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 42. load transient response with overshoot reduction function disabled, gpu mode, v in = 12v, vid = 0.9v, i o = 12a/22a, di/dt = ?fastest? figure 43. cpu mode vid tran sition, dprslpvr = 0, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 figure 44. gpu mode vid transition, dprslpvr = 0, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 typical performance (continued)
isl62881, isl62881b 33 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6924.3 june 16, 2011 for additional products, see www.intersil.com/product_tree figure 45. cpu mode vid tran sition, dprslpvr = 1, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 figure 46. gpu mode vid transition, dprslpvr = 1, i o =2a, vid = 1.2375v/1.0375v, ch2: v o , ch3: vid4 typical performance (continued)
isl62881, isl62881b 34 fn6924.3 june 16, 2011 package outline drawing l28.4x4 28 lead thin quad flat no-lead plastic package rev 0, 9/06 typical recommended land pattern detail "x" top view bottom view notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to amse y14.5m-1994 . 4. bottom side pin#1 id is diepad chamfer as shown. 5. tiebar shown (if present) is a non-functional feature. pin 1 index area 4 . 00 0 ~ 0 . 05 5 0 . 10 pin #1 index area chamfer 0 . 400 x 45 2 . 50 2 . 50 3 . 20 a package boundary 4 . 00 0 . 40 0 . 20 0 . 05 0 . 40 0 . 20 ref 0 . 00 - 0 . 05 see detail x'' seating plane (28x 0 . 60) (0 . 40) (28x 0 . 20) (2 . 50) (2 . 50) (3 . 20) (3 . 20) 0 . 4 x 6 = 2.40 ref 3 . 20 0 . 4 x 6 = 2 . 40 ref max. 0 . 80 (0 . 40) b side view c c 0 . 20 ref 0 . 08 c 0 . 10 c 0 . 10 m c a b 2x 14 8 7 1 28 22 21 15
isl62881, isl62881b 35 fn6924.3 june 16, 2011 package outline drawing l32.5x5e 32 lead thin quad flat no-lead plastic package rev 0, 03/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view ( 4.80 ) (3.70 ) ( 32 x 0.60) (32x 0.25) ( 28x 0.50) ( 4.80 ) ( 3.50) ( 3.50) c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 25 pin #1 index area 32 3.50 28x 0.50 exp. dap 8 1 24 16 32x 0.40 9 6 3.50 3.70 0.10 32x 0.25 a mc b 4 3.70 exp. dap 17 5.00 a b 5.00 (4x) 0.15 6 pin 1 index area max 0.80 see detail "x" seating plane 0.08 0.10 c c c side view

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